// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// Generated by Quartus II 64-Bit Version 13.0 (Build Build 232 06/12/2013)
// Created on Wed May 25 22:17:33 2016

dds_PSK dds_PSK_inst
(
	.clkfc(clkfc_sig) ,	// input  clkfc_sig
	.rst_n(rst_n_sig) ,	// input  rst_n_sig
	.date_sin_100k(date_sin_100k_sig) 	// output [13:0] date_sin_100k_sig
);

